1. Field of the Invention
The present invention relates generally to the field of power semiconductor devices and, more particularly, to a method for fabricating a super-junction power semiconductor device.
2. Description of the Prior Art
As known in the art, power semiconductor devices are mainly used in power management; for instance, in switching power supplies, in management integrated circuits in the core or peripheral regions of computers, in backlight power supplies, and in electric motor controls. This type of power semiconductor devices, as described above, includes an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field effect transistor (MOSFET), or a bipolar junction transistor (BJT), among which the MOSFET is the most widely utilized because of its energy saving properties and its ability to provide faster switch speed.
In one kind of power MOSFET device, a P-type epitaxial layer and an N-type epitaxial layer are alternatively disposed to form vertical PN junctions inside an array of a substrate structure, and the junctions are perpendicular to the surface of the substrate structure. A structure comprising said described PN junctions is called a vertical super-junction structure. In a conventional method for fabricating the super-junction structure, an epitaxial layer of a first conductivity type, e.g. N-type, is formed on a substrate of the first conductivity type. Then, a plurality of trenches are etched into the first conductivity type epitaxial layer. P type dopants are then implanted into the sidewalls of the trenches at oblique angles. After thermal drive-in process, a plurality of vertical PN junctions are formed, comprising a P type body doping region surrounding each of the trenches and the N type semiconductor layer.
The above-described prior art method has still several drawbacks. For instance, it is usually necessary to use the tilt-angle ion implantation for successfully implanting dopants into the sidewalls of the trenches. Typically, the ion implantation angle is no less than 7°. However, under such conditions, the dimensions of the trenches are limited and are not shrinkable. Therefore, the above-described prior art method is not suited for the manufacture of high aspect-ratio deep-trench type power devices. It is desirable to provide an improved method for fabricating super-junction power semiconductor devices that is capable of avoiding the aforesaid problem.